library verilog;
use verilog.vl_types.all;
entity lab2_fre_div4_021 is
    port(
        B2_021          : out    vl_logic;
        CLK_021         : in     vl_logic;
        pin_name1       : out    vl_logic;
        pin_name2       : out    vl_logic
    );
end lab2_fre_div4_021;
